(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method use to fabricate dynamic random access memory, (DRAM), cells, on silicon on insulator, (SOI).
(2) Description of Prior Art
Major objectives of the semiconductor industry have been to increase device performance, while still increasing device density. The use of silicon on insulator, (SOI), layers, have allowed these objectives to be successfully addressed. Performance degrading, junction capacitances, have been minimized, when placing active device regions, such as source/drain regions, in an SOI layer. In addition the use of forming devices, such as a DRAM device, in a SOI layer, allows fully isolated transistors, and cells, to be formed without the use of area consuming, conventional isolation structures, such as insulator filled shallow trench region, or field oxide regions, thus allowing DRAM semiconductor chips, with densities greater than a gigabit bit, to be achieved. However the attainment of high quality SOI layers, to accommodate the high performance devices, can be difficult to achieve.
Prior art, such as Hsu et al, in U.S. Pat. No. 5,610,087, describe the formation of both lateral, bipolar junction devices, as well as metal oxide semiconductor field effect transistors, (MOSFET), in an SOI layer. However that prior art forms the critical SOI layer via a SIMOX, (Separation by Implanted Oxygen), process, which results in a blanket SOI layer, at a thickness between about 1000 to 2000 Angstroms, and presenting a defect density of less than about 1E4 defects /cm.sup.2. This invention will present a novel approach for the attainment of the SOI layer, and the trimming the SOI layer, to create segments of SOI layers, used only to accomodate the active device regions, thus allowing improved device density to be accomplished. A major feature of this invention is the initiation of the single crystalline silicon layer, (SOI layer), via deposition of an amorphous, or polysilicon layer, followed by an anneal cycle, resulting in the initiation of the of the SOI layer in a central node region of the semiconductor substrate, a region exposed in an opening in an insulator layer. The formation of the SOI layer is then continued by the extension of this layer, upwards from the opening in the insulator layer, and extending laterally, overlying a specific portion of the underlying insulator layer, terminating at a specific distance from the opening, or central node region, from which the SOI layer initiated. Trimming of the SOI layer, via oxidation of unwanted regions of the SOI layer, results in the formation of individual SOI segments, used to accomodate the sub-micron DRAM devices, used for the gigabit or greater, DRAM chips.